1. Field of the Invention
The present invention relates to a thin film capacitor used as a stacked capacitor in a memory cell of a dynamic random access memory (DRAM) device.
2. Description of the Related Art
Generally, in a DRAM cell, a stacked capacitor is comprised of a lower electrode made of polycrystalline silicon, an upper electrode layer made of polycrystalline silicon, and a capacitor insulating (dielectric) layer made of silicon oxide or silicon oxide/silicon nitride/silicon oxide (ONO) therebetween. In this case, the permittivity of silicon oxide or ONO is relatively small.
Recently, as DRAM devices have become more fine-structured, stacked capacitors have also become more fine-structured. Particularly, in a 256 Mbit DRAM device where a 0.3 to 0.35 cm rule will be adopted, if silicon oxide or ONO is used as a capacitor dielectric layer, the capacitor insulating layer will be less than 4 nm in thickness, which is difficult to form. Therefore, in order to enhance the capacitance of a stacked capacitor, a high dielectric constant layer has been used as a capacitor dielectric layer made of SiTiO.sub.3 or (Ba, Sr) TiO.sub.3 (BST).
A first prior art stacked capacitor includes a lower electrode layer made of noble metal/refractory metal or conductive oxide/refractory metal such as Pt/Ta and RuO.sub.2 /TiN formed on a polycrystalline silicon plug, an upper electrode layer, and a high dielectric constant layer made of SiTiO.sub.3 or BST therebetween (see: P-Y. Lesaicherre el al. "A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SiTiO.sub.3 and RIE patterned RuO.sub.2 /TiN storage nodes", IEDM, pp. 831-834, 1994). This will be explained later in detail. In this case, the noble metal or conductive oxide hardly reacts with oxygen in an oxygen atmosphere for forming the high dielectric constant layer, and therefore, a low permittivity oxide layer is hardly created between the noble metal and the high dielectric constant layer. Thus, the noble metal or conductive oxide serves as an oxidation resistance conductive layer. However, the noble metal or conductive oxide easily reacts with silicon at a low temperature such as 450.degree. C. to form metal silicide which is easily changed to a low permittivity oxide. Therefore, the refractory metal is inserted between the noble metal or conductive oxide and the polycrystalline silicon plug so that the noble metal or conductive oxide is not in direct contact with the polycrystalline silicon plug. In this case, the refractory metal hardly reacts with silicon even at a temperature of 600.degree. C., so that refractory metal silicide is hardly created. Thus, the refractory metal serves as a silicon diffusion preventing conductive layer.
Note that there has never been a conductive layer which can serve as an oxidation resistance conductive layer as well as a silicon diffusion preventing conductive layer.
In the above-described first prior art stacked capacitor, however, since the refractory metal is exposed to oxygen at a temperature of about 600.degree. C. for forming the high dielectric constant layer, the refractory metal easily reacts with oxygen so that the refractory metal is oxidized. As a result, a contact resistance of the lower electrode layer is increased, and the capacitance density of the stacked capacitor is decreased.
In a second prior art stacked capacitor, in order to avoid oxidation of the refractory metal, an insulating spacer is formed on the entire sidewall of the lower electrode layer prior to the formation of the high dielectric constant layer (see: T. Emori et al., "A Newly Designed Planar Stacked Capacitor Cell with High dielectric Constant Film for 256 Mbit DRAM", IEDM, pp. 631-634, 1993). This also will be explained later in detail.
In the above-described second prior art stacked capacitor, however, the lateral length of the stacked capacitor is substantially increased, which reduces the integration. Particularly, in a 1 Gbit DRAM device where a less than 0.2 .mu.m rule will be adoped, since the physical size of the high dielectric constant layer is limited, the lower electrode layer has to be more stereostructured. Also, the thickness of the oxidation resistance conductive layer is relatively small due to the sidewall insulating spacer, so that a surface area of the oxidation resistance conductive layer in contact with the high dielectric constant layer is small, and thus, a large capacitance cannot be expected.